This PLL IP is an ADPLL-based analog/mixed-signal clock generation IP designed for high-speed SoC and ASIC clock-management applications. It operates in normal 1:1 frequency mode, where the output clock frequency follows the input reference-clock frequency. The supported operating frequency range is from 1 GHz to 4.4 GHz.
The PLL consists of a Time-to-Digital Converter (TDC), Frequency Detector (FD), Digital Loop Filter (DLF), 11-bit Digitally Controlled Oscillator (DCO), high-PSRR reference generator, level shifter, optional divide-by-2 path, and feedback path. It provides differential output clocks through PLL_CLK[1:0] and supports frequency setting, loop-gain adjustment, oscillator calibration, BIST, and test-control functions.
The IP is designed for Samsung Foundry 28 nm LPP process with M1–M6 + IA/IB metal stack option. It is suitable for high-speed clock regeneration, phase alignment, and low-jitter clock distribution in digital and mixed-signal SoC systems.
Feature
· ADPLL-based analog/mixed-signal PLL IP for high-speed SoC clock generation
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Designed for Samsung Foundry 28 nm LPP process
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M1–M6 + IA/IB metal-stack option
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Supports input and output clock frequencies from 1 GHz to 4.4 GHz
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Operates in 1:1 frequency mode where output frequency follows input reference-clock frequency
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Provides differential output clock through PLL_CLK[1:0]
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Includes an internally selected divide-by-2 path for extended frequency-range operation
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Employs Time-to-Digital Converter (TDC), Frequency Detector (FD), Digital Loop Filter (DLF), and 11-bit Digitally Controlled Oscillator (DCO)
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Provides direct proportional path for reduced loop latency and improved transient response
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Includes high-PSRR reference generator
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Supports frequency setting, loop-gain adjustment, oscillator calibration, BIST, and test control
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Supply-voltage range: 0.9 V to 1.3 V
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Typical active supply current: approximately 24 mA at 1.1 V and 3.2 GHz
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Target lock time: less than 500 ns at 3.2 GHz
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Target period jitter: less than 400 fs at 3.2 GHz
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Pre-silicon validated using HSPICE transistor-level simulation and behavioral-model simulation
Application
· High-speed SoC clock generation and internal clock regeneration
Business Area
Semiconductor IP, SoC clock management, ASIC clocking, high-speed mixed-signal IC, digital and mixed-signal subsystem integration
Tech Specs
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IP Name :
PLL
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Provider :
ONE Semiconductor
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Foundry :
SAMSUNG
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Technology :
28nm
Deliverables
· Transistor-level HSPICE netlist
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HSPICE simulation testbenches
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SystemVerilog behavioral model
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PLL IP datasheet
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PLL characterization report
Validation Status
· Pre-silicon simulation-proven
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Validated using transistor-level HSPICE transient simulation and behavioral-model evaluation
Availability
Available for Samsung Foundry 28 nm LPP process only. Delivered as a hard macro with transistor-level HSPICE netlist, simulation testbenches, and SystemVerilog behavioral model.
Benefits
· High-speed clock generation up to 4.4 GHz
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Unity-ratio (1:1) frequency tracking between input and output clock
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Fast lock performance (measured ~72.91 ns, target < 500 ns)
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Low period jitter (target < 400 fs)
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Differential output clock for robust signal integrity
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ADPLL architecture enabling digital control and flexible configuration
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Verified through transistor-level HSPICE simulation and behavioral-model evaluation
