IP 검색 Category Analog & Mixed Signal(29) Memory Controller & PHY(13) Memory & Logic Library(14) Interface Controller & PHY(23) Processor Solutions(39) Arithmetic & Mathematic IP(3) Peripheral(8) Network-on-Chip (NoC)(0) Multimedia(0) Comumnication(0) Platform Level IP(0) Security IP(1) Other IP(0) Software Development & Debug Tool(3) Other(29) Verification IP(12) Palladium(0) Technology 3nm 4nm 5nm 7nm 8nm 10nm 12nm 14nm 16nm 20nm 22nm 28nm 32nm 40nm 45nm 55nm 65nm 90nm 130nm 150nm 180nm 250nm 350nm 500nm FPGA N/A Foundry Others N/A Search IP 전체 제목 내용 검색 전체 140건 현재 페이지 1/35 최신 순 오래된 순 CMSS (CXL Memory Sub-System) CMSS is a Type-2 CXL device-side cache controller that maintains a hardware-coherent device cache over the CXL.cache and CXL.mem protocols. It allows an accelerator such as an NPU or GPU to cache host memory in device-attached DRAM close to computation while remaining fully coherent with the host CPU, removing the need for software-managed coherency. The IP is organized as three cooperating subsystems - a cache datapath (CMSS_CACHE_TOP), a device-attached memory controller (CMSS_MEM_TOP), and a CXL link controller (CMSS_CXL_TOP) - interconnected by credited CPI (CXL Protocol Interface) request, data, and response channels. An accelerator client attaches through a standard AXI4 slave interface, device DRAM attaches through two AXI4 master interfaces for the cache fill/eviction path and the CXL.mem path, configuration is provided through APB slave ports, and the host link is driven through a 4-lane PIPE interface to an external PCIe PHY. 2026-07-31 VPU (Vector Processing Unit) The VPU (Vector Processing Unit) is a SIMD vector accelerator IP that executes BF16 (brain-floating-point 16) vector operations for AI workloads. It receives packed 128-bit vector instructions from a host through a valid/ready request interface, fetches source operands directly from an on-chip Scratchpad Memory (SPM) implemented as SRAM, performs the requested element-wise arithmetic, unary math, or cross-lane reduction operation across parallel vector lanes, and writes the result vector back to the SPM. 2026-07-30 PLL This PLL IP is an ADPLL-based analog/mixed-signal clock generation IP designed for high-speed SoC and ASIC clock-management applications. It operates in normal 1:1 frequency mode, where the output clock frequency follows the input reference-clock frequency. The supported operating frequency range is from 1 GHz to 4.4 GHz. The PLL consists of a Time-to-Digital Converter (TDC), Frequency Detector (FD), Digital Loop Filter (DLF), 11-bit Digitally Controlled Oscillator (DCO), high-PSRR reference generator, level shifter, optional divide-by-2 path, and feedback path. It provides differential output clocks through PLL_CLK[1:0] and supports frequency setting, loop-gain adjustment, oscillator calibration, BIST, and test-control functions. The IP is designed for Samsung Foundry 28 nm LPP process with M1–M6 + IA/IB metal stack option. It is suitable for high-speed clock regeneration, phase alignment, and low-jitter clock distribution in digital and mixed-signal SoC systems. 2026-07-24 LPDDR4/X PHY(for palladium emulation only) This IP is an LPDDR4/LPDDR4X PHY developed by our team based on LiteDRAM. It extends the LiteDRAM-based architecture with our own design and integration to support controller-side DFI interfacing, command/data serialization, and LPDDR4/LPDDR4X physical signaling for emulation-oriented system validation. 2026-03-26 처음으로 이전페이지 1 2 3 4 5 6 7 8 9 10 >다음페이지 마지막으로
