IP 검색 Category Analog & Mixed Signal(29) Memory Controller & PHY(13) Memory & Logic Library(14) Interface Controller & PHY(22) Processor Solutions(38) Arithmetic & Mathematic IP(3) Peripheral(8) Network-on-Chip (NoC)(0) Multimedia(0) Comumnication(0) Platform Level IP(0) Security IP(1) Other IP(0) Software Development & Debug Tool(3) Other(29) Verification IP(12) Palladium(0) Technology 3nm 4nm 5nm 7nm 8nm 10nm 12nm 14nm 16nm 20nm 22nm 28nm 32nm 40nm 45nm 55nm 65nm 90nm 130nm 150nm 180nm 250nm 350nm 500nm FPGA N/A Foundry Others N/A Search IP 전체 제목 내용 검색 전체 138건 현재 페이지 2/35 최신 순 오래된 순 Compact Half-Rate Receiver Front-Ends Quarter-Rate Receiver This IP is compact single-ended receiver front-ends generated by layout generator software. This IP adopts quarter-rate architecture. The front-ends uses half-VDD termination and received bit errors can be checked and counted real time by PRBS Checker. Termination resistance can be tuned using resistor bank controlled by digital bits. Slicers reference voltage can be controlled by external analog voltage input. Precise control for duty cycle and quarter-rate phase mismatch can be achieved by DCC and QEC blocks. The front end’s generation time is only 0.719s which is 240000 times fast than manual layout. 2026-02-27 Compact Quarter-Rate Receiver Front-Ends Quarter-Rate Receiver This IP is compact single-ended receiver front-ends generated by layout generator software. This IP adopts quarter-rate architecture. The front-ends uses half-VDD termination and received bit errors can be checked and counted real time by PRBS Checker. Termination resistance can be tuned using resistor bank controlled by digital bits. Slicers reference voltage can be controlled by external analog voltage input. Precise control for duty cycle and quarter-rate phase mismatch can be achieved by DCC and QEC blocks. The front end’s generation time is only 0.732s which is 240000 times fast than manual layout. 2026-02-27 112G VSR PAM-4 SERDES PHY (차세대지능형반도체사업단) 112Gbps PAM-4 SERDES PHY for VSR (Very Short Reach) Compliant to CEI-112G-VSR standard 2026-02-10 FlexNPUSim (차세대지능형반도체사업단) ■ Neural Processor Unit(NPU)와 시스템 간 상호작용을 시뮬레이션하여 다양한 NPU 아키텍처의 성능을 효율적으로 분석하는 성능 시뮬레이터 ■ Deep Neural Network(DNN) 연산을 수행하는 NPU의 다양한 연산 동작을 6~9개의 파라미터(입출력 관계 및 계산 지연시간)로 모델링해 여러 NPU 아키텍처에 대한 성능 분석을 가능하게 하는 시뮬레이터 2026-02-06 처음으로 이전페이지 1 2 3 4 5 6 7 8 9 10 >다음페이지 마지막으로
