IP 검색 Category Analog & Mixed Signal(29) Memory Controller & PHY(13) Memory & Logic Library(14) Interface Controller & PHY(22) Processor Solutions(38) Arithmetic & Mathematic IP(3) Peripheral(8) Network-on-Chip (NoC)(0) Multimedia(0) Comumnication(0) Platform Level IP(0) Security IP(1) Other IP(0) Software Development & Debug Tool(3) Other(29) Verification IP(12) Palladium(0) Technology 3nm 4nm 5nm 7nm 8nm 10nm 12nm 14nm 16nm 20nm 22nm 28nm 32nm 40nm 45nm 55nm 65nm 90nm 130nm 150nm 180nm 250nm 350nm 500nm FPGA N/A Foundry Others N/A Search IP 전체 제목 내용 검색 전체 138건 현재 페이지 9/35 최신 순 오래된 순 Analog op-amp This Operational Amplifier IP is a fully analog, low-power, differential-input, single-ended-output amplifier designed for integration in mixed-signal and low-voltage SoC platforms. It amplifies the differential voltage between two input nodes (VIN+ and VIN−) and provides a single-ended output (VOUT), making it suitable for use in ADC drivers, sensor interfaces, and general-purpose analog signal conditioning. The op-amp operates with a single supply voltage. It includes differential input stages, high-gain amplification paths, and miller compensation network to ensure stable operation with closed loop configuration. Structurally, the amplifier consists of a PMOS input differential pair with active current mirror loads, followed by a single-ended gain stage that converts the differential signal to a single-ended output. A Miller or feedforward compensation path is included to guarantee sufficient phase margin in unity-gain buffer configuration and other closed-loop applications. The amplifier is designed for use in both open-loop and closed-loop configurations. In closed-loop use, the feedback network determines the effective gain, while the amplifier ensures linearity and stability. No digital inputs or control interfaces are required, and the amplifier responds continuously to analog input variations. 2025-07-02 Voltage comparator The ‘Voltage comparator’ is an analog IP block that accepts two analog voltage inputs: INP (positive input) and INN (negative input). It evaluates the polarity of the differential input voltage (INP - INN) and produces a differential digital output through OUTP and OUTN nodes. The comparison process is gated by a digital control signal, EN, which acts as a clock or trigger. Upon receiving a rising edge or high-level pulse at EN, the comparator enters an evaluation phase, internally activates the decision circuitry, and latches the result based on the instantaneous differential input. The output is inversed signal versus EN. The output settles quickly to a valid logic level using an internal regenerative latch, providing robust and noise-immune decisions even under small input differences. Fabricated in a 28nm CMOS Low power process. 2025-07-02 파워업 감지회로 The Power-On Reset (POR) circuit is an analog IP designed to generate a reliable reset signal during both power-up and power-down sequences. Implemented in a standard CMOS process, this IP ensures that digital and mixed-signal systems remain in a known safe state until the supply voltage reaches a stable threshold, enabling robust startup behavior across a wide range of conditions. The POR IP is composed entirely of analog building blocks and requires no external clock, biasing, or digital input control. It receives a single analog input (VDD) and outputs a digital reset signal (VOUT). The core signal path consists of a voltage divider, temperature compensator, and reset signal generator. The voltage divider provides a scalable reference for comparison, while the temperature compensator suppresses variations in threshold voltage due to temperature changes. The reset signal generator includes a carefully sized inverter chain with embedded hysteresis for stable switching behavior. The circuit is designed to generate the reset signal when the supply voltage crosses a defined rising threshold during power-up, and to reassert the reset during power-down when the voltage drops below a falling threshold. The built-in hysteresis ensures noise immunity and eliminates false resets due to supply ripples or slow ramping. 2025-07-02 Voltage reference This Bandgap Reference (BGR) IP is an ultra-low-power, sub-1V analog voltage reference generator designed for integration in advanced mixed-signal SoCs. It generates temperature- and supply-stable reference voltage suitable for low-voltage, low-power applications such as biomedical front ends, IoT sensor nodes, and DRAM PIM systems. The IP operates entirely in the analog domain, taking a single supply voltage as input and producing a precise reference voltage output. It does not require any digital control interface. Internally, it includes a proportional-to-absolute-temperature (PTAT) current generator, a complementary-to-absolute-temperature (CTAT) reference path, and a high-gain two-stage operational amplifier. A dedicated startup circuit ensures reliable initialization under all process, voltage, and temperature conditions. The feedback structure enhances loop stability and provides strong immunity against supply and temperature variations. The design emphasizes high PSRR and a low temperature coefficient, supporting robust performance in environments with fluctuating supply and ambient conditions. The IP is implemented in a standard CMOS process and features a compact layout area, making it well-suited for highly integrated, battery-powered systems and always-on analog blocks. 2025-07-02 처음으로 이전페이지 4 5 6 7 8 9 10 11 12 13 >다음페이지 마지막으로
