IP 검색 Category Analog & Mixed Signal(13) Memory Controller & PHY(0) Memory & Logic Library(7) Interface Controller & PHY(0) Processor Solutions(3) Arithmetic & Mathematic IP(0) Peripheral(1) Network-on-Chip (NoC)(0) Multimedia(0) Comumnication(0) Platform Level IP(0) Security IP(1) Other IP(0) Software Development & Debug Tool(1) Other(83) Verification IP(0) Technology 3nm 4nm 5nm 7nm 8nm 10nm 12nm 14nm 16nm 20nm 22nm 28nm 32nm 40nm 45nm 55nm 65nm 90nm 130nm 150nm 180nm 250nm 350nm 500nm FPGA N/A Foundry Others N/A Search IP 전체 제목 내용 검색 전체 109건 현재 페이지 5/28 Analog Convolution Network Accelerator Block (차세대지능형반도체사업단) · CNN Model (YOLOv2 등)을 초저전력 가속기 SoC로 구현하기 위한 Analog Convolutional Filter를 병렬 연결하여 고속 inference 지원 · Hard Core IP (TSMC 55nm/65nm 기반 설계), Soft Core: RTL 2024-08-29 Analog op-amp This Operational Amplifier IP is a fully analog, low-power, differential-input, single-ended-output amplifier designed for integration in mixed-signal and low-voltage SoC platforms. It amplifies the differential voltage between two input nodes (VIN+ and VIN−) and provides a single-ended output (VOUT), making it suitable for use in ADC drivers, sensor interfaces, and general-purpose analog signal conditioning. The op-amp operates with a single supply voltage. It includes differential input stages, high-gain amplification paths, and miller compensation network to ensure stable operation with closed loop configuration. Structurally, the amplifier consists of a PMOS input differential pair with active current mirror loads, followed by a single-ended gain stage that converts the differential signal to a single-ended output. A Miller or feedforward compensation path is included to guarantee sufficient phase margin in unity-gain buffer configuration and other closed-loop applications. The amplifier is designed for use in both open-loop and closed-loop configurations. In closed-loop use, the feedback network determines the effective gain, while the amplifier ensures linearity and stability. No digital inputs or control interfaces are required, and the amplifier responds continuously to analog input variations. 2025-07-02 Auto focus algorithm unit (차세대지능형반도체사업단) · Auto focus기능을 내장한 Lens를 이용하여 피사체 및 배율에 따라 Auto Focus를 구현하는 Unit 2024-08-30 BBCDR for multi-rate high speed SerDes receiver (차세대지능형반도체사업단) · PCIe interface system 지원 가능한 Multi-rate BBCDR 2024-08-29 처음으로 이전페이지 1 2 3 4 5 6 7 8 9 10 >다음페이지 마지막으로
