IP 검색 Category Analog & Mixed Signal(29) Memory Controller & PHY(13) Memory & Logic Library(14) Interface Controller & PHY(22) Processor Solutions(38) Arithmetic & Mathematic IP(3) Peripheral(8) Network-on-Chip (NoC)(0) Multimedia(0) Comumnication(0) Platform Level IP(0) Security IP(1) Other IP(0) Software Development & Debug Tool(3) Other(29) Verification IP(12) Palladium(0) Technology 3nm 4nm 5nm 7nm 8nm 10nm 12nm 14nm 16nm 20nm 22nm 28nm 32nm 40nm 45nm 55nm 65nm 90nm 130nm 150nm 180nm 250nm 350nm 500nm FPGA N/A Foundry Others N/A Search IP 전체 제목 내용 검색 전체 138건 현재 페이지 10/35 최신 순 오래된 순 Supply regulator The “Supply regulator” is a fully integrated NMOS-based linear regulator designed for ultra-low input voltage operation. The core of the LDO comprises an NMOS pass transistor, an error amplifier (EA), and a charge pump-based gate voltage booster known as the invert-phase synchronized self-oscillating charge pump (I-SOCP). This architecture enables the system to regulate output voltage with a dropout voltage well below the threshold voltage of the pass transistor, even under supply voltages below 1V. The NMOS pass transistor is driven by a gate voltage (VG) generated by the I-SOCP, which operates without an external clock and maintains VG above the input voltage. This elevated VG allows the NMOS transistor to enter the triode region and minimize the dropout voltage. Simultaneously, the I-SOCP output is used as the supply for the EA, thereby ensuring adequate headroom and linear regulation even under sub-1V input conditions. Unlike conventional LDOs with step-up charge pumps, the proposed architecture does not require large flying or output capacitors. Instead, the gate capacitance of the pass transistor is used directly, reducing area and power overhead. The I-SOCP operates in a self-oscillating and phase-synchronized manner, which improves the voltage boosting capability by enabling both rising and falling edge operations of internal nodes. This NMOS LDO is ideal for low-power SoC platforms where minimal dropout and high efficiency under low voltage supplies are critical. Its fully analog regulation, self-oscillating clock generation, and compact capacitor-less boosting structure make it suitable for integration in advanced battery-powered systems. 2025-07-02 Hybrid D-FF The Hybrid D Flip-Flop (Hybrid D-FF) is a compact, low-power, fully digital sequential logic IP designed for near-threshold computing (NTC) systems. It is implemented in a 28 nm low-power CMOS process and operates reliably down to 0.25 V, making it ideal for energy-efficient SoCs and low-voltage digital platforms. The flip-flop is fully compatible with standard digital design flows and require no external biasing or control signals beyond the clock (CK) and data (D) inputs. This flip-flop features a hybrid architecture that combines the robustness of transmission-gate flip-flops (TGFF) with the speed and simplicity of true single-phase clock (TSPC) logic. The design utilizes both feedback and feedforward paths to improve data stability and reduce output delays. The input (D) is sampled on the rising edge of the clock (CK), and the output (Q) is updated accordingly. No asynchronous set or reset is included, allowing for minimal area and power overhead. Structurally, the Hybrid-FF is composed of a small number of transistors (20 total, including clock inverters), a split TSPC-style latch, and a compact clocking scheme that ensures full voltage transitions without contention. The latch stage employs a feedback loop for stability and a carefully tuned capacitance path to minimize clock-to-Q delay. Architecture eliminates the Vth drop issue commonly found in TSPC designs and ensures full-swing outputs under low voltage. 2025-07-02 SAR ADC The ‘SAR ADC’ is a compact, low-power, and digitally controlled analog-to-digital converter IP optimized for in-memory computing (PIM) applications. Designed in 28 nm CMOS, this IP supports dynamic reconfiguration of both bandwidth and resolution to efficiently adapt to different modes of operations such as inference and training—in AI and edge SoCs. The ADC operates based on a 5-bit capacitive DAC (CDAC) core, sampling analog inputs through a bootstrapped switch and processing them with a 2-stage dynamic comparator. Output data is provided in a digital format through internal SAR logic. 2025-07-02 CML-to-CMOS The CML2CMOS is a compact converter IP that translates differential current-mode logic (CML) clock signals into full-swing CMOS levels. Fabricated in a 28 nm CMOS process, it supports output clock frequencies up to 1.87 GHz while consuming less than 0.5 mW. The IP receives differential CML inputs and converts them into CMOS logic outputs using a two-stage architecture. Each stage consists of a current-steering differential pair that performs differential-to-single-ended conversion and is followed by a CMOS inverter buffer. The same structure is duplicated across phases to produce four-phase outputs: ICLK, IBCLK, QCLK, and QBCLK. This ensures matched delay paths and balanced timing across all phases. The converter supports basic bias-based configurability through an external analog control voltage, “VB”, that sets the tail current of the differential pair. This mechanism allows limited tuning of delay and power characteristics to adapt to different operating conditions. Designed for robustness and compactness, the CML2CMOS block is suitable for clock signal reception and level translation in differential clock distribution paths such as memory interfaces, SerDes, and other high-speed clocking architectures. 2025-06-24 처음으로 이전페이지 5 6 7 8 9 10 11 12 13 14 >다음페이지 마지막으로
