IP 검색 Category Analog & Mixed Signal(29) Memory Controller & PHY(13) Memory & Logic Library(14) Interface Controller & PHY(23) Processor Solutions(39) Arithmetic & Mathematic IP(3) Peripheral(8) Network-on-Chip (NoC)(0) Multimedia(0) Comumnication(0) Platform Level IP(0) Security IP(1) Other IP(0) Software Development & Debug Tool(3) Other(29) Verification IP(12) Palladium(0) Technology 3nm 4nm 5nm 7nm 8nm 10nm 12nm 14nm 16nm 20nm 22nm 28nm 32nm 40nm 45nm 55nm 65nm 90nm 130nm 150nm 180nm 250nm 350nm 500nm FPGA N/A Foundry Others N/A Search IP 전체 제목 내용 검색 전체 140건 현재 페이지 13/35 최신 순 오래된 순 Voltage-to-Time Converter The Voltage-to-Time Converter (VTC) is a high-speed, low-power, and variation-tolerant IP which generates a time-domain output pulse PVTC proportional to the voltage difference between two analog voltage inputs VIN and VREF (Figure 1). The VTC generates a timing pulse based on the delay caused by charging a capacitor from VIN until it reaches an inverter’s threshold. By subtracting a pulse proportional to VREF from this timing pulse, a final output pulse PVTC proportional to VIN – VREF is obtained. The IP includes a power-saving mode enabled via specific clock phase state, significantly reducing power consumption when inactive. Fabricated in a 28 nm CMOS process and occupying only 28 μm² of core area, the VTC is ideal for integration into power-sensitive and space-constrained mixed-signal systems. Designed for robustness across varying environmental conditions, the VTC offers excellent tolerance to supply voltage and temperature fluctuations, with output pulse variation maintained within tens of picoseconds across the full operating range. It supports high-frequency operation exceeding 10 MHz, making it suitable for fast, event-driven applications. 2025-06-24 4-Bit Capacitive DAC The 4-bit capacitive DAC is a monolithic, ultra-low power digital-to-analog converter silicon IP implemented in a 28nm CMOS process. It features a single-ended charge-redistribution architecture based on binary-weighted metal–oxide–metal (MOM) capacitors, optimized for compact area. The output is delivered in a binary-weighted voltage format. 2025-06-24 5-B Flash ADC The Flash ADC is a monolithic, high-speed, low-latency analog-to-digital converter silicon IP optimized for applications requiring ultra-fast signal acquisition and minimal conversion delay. Utilizing a fully parallel architecture, the IP achieves one-clock-cycle conversion by simultaneously comparing the single-ended input signal (IN) against voltage reference using the array of 2^5-1 high-speed clocked comparators. Reference voltages for comparator array are generated by external resistor ladder with bias. The IP includes thermometer-to-binary encoding for making 5bit digital output (OUT). It supports high-frequency sampling up to 200MHz. Fabricated in a 28 nm CMOS process, the IP occupies 0.04mm2 of core area. 2025-06-23 Resistance Implementation in Phase-Change Memory Precise resistance control in Phase-Change Random Access Memory (PRAM) by adjusting pulse parameters such as amplitude, trailing edge, and delay. 2025-03-10 처음으로 이전페이지 8 9 10 11 12 13 14 15 16 17 >다음페이지 마지막으로
