IP 검색 Category Analog & Mixed Signal(29) Memory Controller & PHY(13) Memory & Logic Library(14) Interface Controller & PHY(22) Processor Solutions(38) Arithmetic & Mathematic IP(3) Peripheral(8) Network-on-Chip (NoC)(0) Multimedia(0) Comumnication(0) Platform Level IP(0) Security IP(1) Other IP(0) Software Development & Debug Tool(3) Other(29) Verification IP(12) Palladium(0) Technology 3nm 4nm 5nm 7nm 8nm 10nm 12nm 14nm 16nm 20nm 22nm 28nm 32nm 40nm 45nm 55nm 65nm 90nm 130nm 150nm 180nm 250nm 350nm 500nm FPGA N/A Foundry Others N/A Search IP 전체 제목 내용 검색 전체 138건 현재 페이지 8/35 최신 순 오래된 순 Level Shifter • The proposed level shifter, named the diode-connected cross coupled pFET level shifter with staked split-input inverter (DCPLS-SSI) is a wide-range voltage conversion and energy-efficient solution for DRAM voltage conversion in 28 nm CMOS technology. The proposed level shifter can mitigate the current contention by using diode-connected cross coupled pFET structure, which enables wide-range voltage conversion. In addition, the stacked split-input inverter can reduce the short-circuit current of output inverter, which enable energy-efficient operation. 2025-07-04 I/O Sense Amplifier • The proposed sense amplifier, named the Static Current-Free Pre-Sensing IO Sense Amplifier (SCFP-IOSA), is a high-speed, low-power sensing solution for DRAM global I/O in 28 nm CMOS technology. It employs a direct input transfer architecture using a single coupling capacitor (CC) and introduces a static current-free pre-sensing technique to minimize offset voltage (VOS), area, and energy overhead. Unlike conventional offset cancellation (OC)-based I/O sense amplifiers, which suffer from input voltage attenuation, large area due to dual CCs, and static current during sensing, SCFP-IOSA eliminates attenuation by directly transferring the input differential voltage (ΔVGIO) and avoids static current using exponential RC pre-amplification. The proposed design separates ΔVGIO generation and sensing by GIO switches, allowing simultaneous offset cancellation and input development. This reduces sensing time overhead and enables a fast sensing time of 3.75 ns, with 2.15 μW power consumption, and 10.28 μm² area, achieving 3× lower σVOS, 2.9× lower power, and 4.46× smaller area compared to state-of-the-art OC-IOSA. Moreover, it shows robust sensing yield even in noisy conditions, and maintains performance at low supply voltages. These characteristics make SCFP-IOSA highly suitable for next-generation low-voltage, high-density DRAM applications, particularly in 1Ynm-class or beyond. 2025-07-04 BL Sense Amplifier • The proposed sense amplifier, named the Dual-Input Stacked Inverter-Based Single-Ended DRAM Sense Amplifier (DISA), is a monolithic, low-power, high-speed sensing solution for DRAMs fabricated in 28 nm CMOS technology. It employs a dual-input stacked inverter architecture with bit-line (BL) switches and a single-ended structure to minimize area, power, and timing overhead. Unlike conventional bit-line sense amplifiers (BLSAs) that rely on differential coupling capacitors and require a dedicated offset-cancellation (OC) phase, DISA performs offset cancellation and charge sharing simultaneously. This eliminates the timing penalty from OC time and enables the fastest sensing operation, achieving sensing times of less than 9 ns at 0.7 V and less than 8 ns at 0.8 V, defined as the time when BL and BLB reach 80% and 20% of VDD, respectively. Thanks to its single-ended topology and use of only one coupling capacitor, DISA occupies the smallest area among compared designs and supports high-density DRAM layouts with sub-50 nm bit-line pitch. The dual-input stacked inverter enhances gain by using stacked transistors operating in the linear region, significantly reducing static current in both the OC and main sensing phases. In addition, direct BL connection to the IN node improves noise immunity by avoiding floating nodes and ensuring robust sensing even under process scaling and voltage reduction. Overall, DISA demonstrates superior energy efficiency, achieving the lowest measured sensing energy of 5.8 fJ/cycle/bit, and supports low-voltage operation down to 0.55 V, making it highly suitable for advanced low-power DRAM applications. 2025-07-04 Unity-gain buffer The "Unity-Gain Buffer" is a low-power, fully differential analog buffer IP designed for high-speed, low-distortion applications requiring voltage following with minimal offset and excellent linearity. The IP is composed of a differential-input, single-ended-output operational amplifier configured in a unity-gain feedback topology. Users must connect ‘Analog op-amp’ IP’s ports both VINN and VOUT together to use ‘Unity-Gain Buffer’. The analog IP receives an input signal and outputs a single-ended signal that follows input signal. Internally, the design includes a compensation network optimized for unity-gain stability, ensuring no oscillation. Structurally, the amplifier consists of a PMOS input differential pair with active current mirror loads, followed by a single-ended gain stage that converts the differential signal to a single-ended output. A Miller or feedforward compensation path is included to guarantee sufficient phase margin in unity-gain buffer configuration and other closed-loop applications. The buffer is designed with the feedback network determines the effective gain, while the amplifier ensures linearity and stability. No digital inputs or control interfaces are required, and the amplifier responds continuously to analog input variations. The IP Implemented in a 28 nm CMOS low power process. 2025-07-02 처음으로 이전페이지 3 4 5 6 7 8 9 10 11 12 >다음페이지 마지막으로
