IP 검색 Category Analog & Mixed Signal(29) Memory Controller & PHY(13) Memory & Logic Library(14) Interface Controller & PHY(22) Processor Solutions(38) Arithmetic & Mathematic IP(3) Peripheral(8) Network-on-Chip (NoC)(0) Multimedia(0) Comumnication(0) Platform Level IP(0) Security IP(1) Other IP(0) Software Development & Debug Tool(3) Other(29) Verification IP(12) Palladium(0) Technology 3nm 4nm 5nm 7nm 8nm 10nm 12nm 14nm 16nm 20nm 22nm 28nm 32nm 40nm 45nm 55nm 65nm 90nm 130nm 150nm 180nm 250nm 350nm 500nm FPGA N/A Foundry Others N/A Search IP 전체 제목 내용 검색 전체 138건 현재 페이지 35/35 최신 순 오래된 순 Dynamic Voltage Scaling Digital-LDO · LDOs are actively used in recent high-performance processors, low-power processors, and SoCs due to their advantages of a small footprint and clean output voltage. In pursuit of efficient design in terms of chip area and power consumption, LDOs are sometimes integrated into SoCs. However, with the ongoing trend of advancing manufacturing processes, traditional Analog-LDOs face challenges in designing at lower VDD levels in fine processes, posing difficulties for SoCs integration. On the other hand, Digital-LDOs leverage the benefits of fine processes, offering improved performance and ease of SoCs integration. 2024-07-24 PLL-based clock generator for PIM · The frequency synthesizer generates a range of frequencies from a single reference frequency, which usually comes from a crystal oscillator. Frequency synthesizers are one of the most critical building blocks in modern electronic devices, such as mobile telephones, laptops, televisions, radiotelephones, satellite communications, GPS systems, etc. One of the popular types of frequency synthesizers is a phase-locked loop (PLL). In Processing-in-Memory (PIM), PLL will be designed and used to synchronize a clock inside the PIM. 2024-07-24 처음으로 이전페이지 26 27 28 29 30 31 32 33 34 35 >다음페이지 마지막으로
