IP 검색 Category Analog & Mixed Signal(29) Memory Controller & PHY(13) Memory & Logic Library(14) Interface Controller & PHY(22) Processor Solutions(38) Arithmetic & Mathematic IP(3) Peripheral(8) Network-on-Chip (NoC)(0) Multimedia(0) Comumnication(0) Platform Level IP(0) Security IP(1) Other IP(0) Software Development & Debug Tool(3) Other(29) Verification IP(12) Palladium(0) Technology 3nm 4nm 5nm 7nm 8nm 10nm 12nm 14nm 16nm 20nm 22nm 28nm 32nm 40nm 45nm 55nm 65nm 90nm 130nm 150nm 180nm 250nm 350nm 500nm FPGA N/A Foundry Others N/A Search IP 전체 제목 내용 검색 전체 138건 현재 페이지 34/35 최신 순 오래된 순 Tensor CACHE (TCACHE) (차세대지능형반도체사업단) · 서버 NPU 연산을 위한 입출력 data를 저장하는 memory · 서버 NPU Subblock IP 2024-08-29 RISC-V · The RISC-V IP is a PIM-friendly top control processor that supports general ISA for non-linear and non-convolution functions. To support both cache coherence and direct communication with PIM, custom-designed cache writes policies of write-through(uncached) and write-back(cached) are supported. 2024-07-26 DSPU · The DSPU IP is a depth signal processor that generates a 3-D depth image from a 2-D image. · The output is a 3-D dense depth image aligned with a 2-D RGB image. · The DSPU IP enables to adjust depth quality, such as resolution, framerate, and power modes, by configuration. 2024-07-26 CI-C SAR ADC · The ADC used in PIM converts analog signals generated from the memory array into digital. To enable simple calibration and porting and to have high area efficiency, it is better to apply the ADC to the memory column in a thin and long form. The SAR ADC IP has a thin width of 10.3um, a conversion rate of 600MSamples per second, and an SNDR of 43.5dB. 2024-07-24 처음으로 이전페이지 26 27 28 29 30 31 32 33 34 35 >다음페이지 마지막으로
