IP 검색 Category Analog & Mixed Signal(29) Memory Controller & PHY(13) Memory & Logic Library(14) Interface Controller & PHY(22) Processor Solutions(38) Arithmetic & Mathematic IP(3) Peripheral(8) Network-on-Chip (NoC)(0) Multimedia(0) Comumnication(0) Platform Level IP(0) Security IP(1) Other IP(0) Software Development & Debug Tool(3) Other(29) Verification IP(12) Palladium(0) Technology 3nm 4nm 5nm 7nm 8nm 10nm 12nm 14nm 16nm 20nm 22nm 28nm 32nm 40nm 45nm 55nm 65nm 90nm 130nm 150nm 180nm 250nm 350nm 500nm FPGA N/A Foundry Others N/A Search IP 전체 제목 내용 검색 전체 138건 현재 페이지 7/35 최신 순 오래된 순 DRAM_PIM Decoder • The row decoder is designed to handle a 9-bit address input, allowing the selection of one out of 512 columns. To control its operation, several global signals are utilized. The Decoder_enable signal ensures that no decoder output is unintentionally activated when no valid address is present, effectively disabling all decoder outputs when needed. The Write/read enable signal determines whether the write word line (WWL) or read word line (RWL) is activated, enabling appropriate access to the cell array. For MAC operations, MAC_enable and MAC_mux signals are used to drive the MAC word line (MWL). Each subarray includes a multiplexer that enables the same cell position across subarrays simultaneously, such as cell<0>, cell<4>, cell<8>, and so on. 2025-07-04 Digital_Post_Accumulator The proposed post-accumulator is used in the MAC operation process, which receives bit-serial input and accumulates the MAC results generated in each cycle by reflecting the bit positions of the 8-bit input activation. This circuit takes a 13-bit MAC result as input, adds it to the result from the previous cycle, and left-shifts the summed result by 1 bit to align with the bit position of the next cycle's input. This process is repeated over 8 cycles, ultimately generating a 20-bit output. The post-accumulator operates with a clock period of 4 ns and a supply voltage of 1.0 V. 2025-07-04 DRAM MAC Processing Unit • This MAC (Multiplication and Accumulation) circuit performs computations on 64 pairs of 8-bit inputs and 8-bit weights. The input values are provided in digital form, and the intermediate computation results are stored as analog voltage levels through capacitive coupling. Once the final analog voltage generation is complete, the result is converted back into an 8-bit digital value using an Analog-to-Digital Converter (ADC), thus completing the computation process. To enable parallel multiplication and accumulation of the 64 input-weight pairs, the MAC circuit is composed of 64 "unit multipliers" connected along a long accumulation line. Each unit multiplier multiplies the same 8-bit input and 8-bit weight. In each unit, the weight is fixed, and the input is streamed in a bit-serial manner, two bits at a time, to perform the multiplication. The multiplication result drives an internal capacitor driver within the multiplier. If the result is 1, the driver induces a voltage change on the accumulation line via capacitive coupling; if the result is 0, no voltage change occurs. This mechanism generates an analog voltage that reflects the accumulated result. To support floating-point computation characteristics, the circuit first determines the maximum exponent among the 64 input-weight pairs. Each unit multiplier receives the exponent difference between its own input-weight pair and this maximum exponent. Based on the received exponent difference, each unit adjusts the timing of input bit streaming to reflect the relative exponent alignment among the floating-point numbers. As a result, the MAC circuit generates an analog voltage in the range of 426 mV to 973 mV, and the ADC quantizes this voltage range into an 8-bit digital output. 2025-07-04 DRAM PIM cell & Array • The proposed processing-in-memory macro is a monolithic, low-power, high-density analog PIM solution fabricated in 28 nm CMOS technology. It features a 4T1C dual-port DRAM cell (DPC) that physically separates the refresh and MAC (multiply-and-accumulate) ports, enabling simultaneous refresh and computation (SMR)—a breakthrough that addresses the refresh bottleneck of prior DRAM-PIM designs. This dual-port structure allows the refresh cycle to proceed independently without stalling MAC operations, significantly improving throughput by 27.5%. The cell is designed with both MOS and MOM capacitors to ensure sufficient data retention time (DRT), while the refresh logic uses a dedicated read bitline and write bitline for non-destructive restoration. 2025-07-04 처음으로 이전페이지 2 3 4 5 6 7 8 9 10 11 >다음페이지 마지막으로
