IP 검색 Category Analog & Mixed Signal(29) Memory Controller & PHY(13) Memory & Logic Library(14) Interface Controller & PHY(23) Processor Solutions(39) Arithmetic & Mathematic IP(3) Peripheral(8) Network-on-Chip (NoC)(0) Multimedia(0) Comumnication(0) Platform Level IP(0) Security IP(1) Other IP(0) Software Development & Debug Tool(3) Other(29) Verification IP(12) Palladium(0) Technology 3nm 4nm 5nm 7nm 8nm 10nm 12nm 14nm 16nm 20nm 22nm 28nm 32nm 40nm 45nm 55nm 65nm 90nm 130nm 150nm 180nm 250nm 350nm 500nm FPGA N/A Foundry Others N/A Search IP 전체 제목 내용 검색 전체 140건 현재 페이지 11/35 최신 순 오래된 순 SAR ADC The ‘SAR ADC’ is a compact, low-power, and digitally controlled analog-to-digital converter IP optimized for in-memory computing (PIM) applications. Designed in 28 nm CMOS, this IP supports dynamic reconfiguration of both bandwidth and resolution to efficiently adapt to different modes of operations such as inference and training—in AI and edge SoCs. The ADC operates based on a 5-bit capacitive DAC (CDAC) core, sampling analog inputs through a bootstrapped switch and processing them with a 2-stage dynamic comparator. Output data is provided in a digital format through internal SAR logic. 2025-07-02 CML-to-CMOS The CML2CMOS is a compact converter IP that translates differential current-mode logic (CML) clock signals into full-swing CMOS levels. Fabricated in a 28 nm CMOS process, it supports output clock frequencies up to 1.87 GHz while consuming less than 0.5 mW. The IP receives differential CML inputs and converts them into CMOS logic outputs using a two-stage architecture. Each stage consists of a current-steering differential pair that performs differential-to-single-ended conversion and is followed by a CMOS inverter buffer. The same structure is duplicated across phases to produce four-phase outputs: ICLK, IBCLK, QCLK, and QBCLK. This ensures matched delay paths and balanced timing across all phases. The converter supports basic bias-based configurability through an external analog control voltage, “VB”, that sets the tail current of the differential pair. This mechanism allows limited tuning of delay and power characteristics to adapt to different operating conditions. Designed for robustness and compactness, the CML2CMOS block is suitable for clock signal reception and level translation in differential clock distribution paths such as memory interfaces, SerDes, and other high-speed clocking architectures. 2025-06-24 CML Driver The CML driver drives two pairs differential CMOS level inputs (inIp & inIn, inQp & inQn) to two pairs of differential current-mode logic outputs (Ioutp & Ioutn, Qoutp & Qoutn) with minimum skew for high speed signal distribution. The CML driver is specifically designed for a clock distribution network for high speed signaling. A bias current is necessary to bias the current sources in the CML driver. The biasing circuitry can be amortized over multiple drivers to minimize the overhead. The device operates from 0.9-V to 1.1-V supply environment and is characterized from –40°C to 125°C. The CML driver employs a fully differential structure in order to maximize the rejection capabilities against common-mode noise and power supply noise. The CML driver has been experimentally verified through its application in LPDDR5 DRAM interface. 2025-06-24 Repeater Chain The Repeater Chain IP is a mixed-signal, high-speed, low-power signal conditioning block designed to restore signal quality across long on-chip interconnects. It consists of a cascaded buffer/inverter architecture that compensates for RC-induced delay and waveform degradation, ensuring clean and reliable digital signal propagation over extended wire lengths. The core employs a multi-stage structure of optimally sized CMOS repeaters, each regenerating the signal and sharpening its transition edges. Input and output are both standard digital logic levels, with the output exhibiting enhanced edge rate and minimized delay skew. The number and placement of repeater stages are tuned based on wire length, capacitive loading, and timing constraints. To support robust operation under process, voltage, and temperature (PVT) variations, the IP optionally integrates control logic for dynamic drive strength adaptation. This ensures consistent performance across corner cases without requiring external calibration. Designed for integration in global SoC routing paths, clock distribution trees, and high-speed data buses, the Repeater Chain IP provides an essential solution for maintaining signal integrity and timing reliability in advanced digital systems. Figure 1 shows the functional block diagram of the repeater chain, including the parasitic load capacitance from the metal line. Implemented in a 28nm standard CMOS process with minimal area and power overhead, it is well suited for power-conscious, high-performance applications. 2025-06-24 처음으로 이전페이지 6 7 8 9 10 11 12 13 14 15 >다음페이지 마지막으로
