The proposed post-accumulator is used in the MAC operation process, which receives bit-serial input and accumulates the MAC results generated in each cycle by reflecting the bit positions of the 8-bit input activation. This circuit takes a 13-bit MAC result as input, adds it to the result from the previous cycle, and left-shifts the summed result by 1 bit to align with the bit position of the next cycle's input. This process is repeated over 8 cycles, ultimately generating a 20-bit output.
The post-accumulator operates with a clock period of 4 ns and a supply voltage of 1.0 V.