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KAIST AI반도체 최고경영자과정 2기 모집 안내
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KAIST AI-PIM PIM반도체연구센터

IP 검색

DVS Low-latency & Multi-mode Event-based Signal Processor (차세대지능형반도체사업단)

■ DVS Interface, Low-latency ER &, ROI IP
■ DVS Event-based Signal Processor

Feature
· ■ VGA or HD Resolution Event-based Vision Sensor
· ■ MIPI CSI-2 Tx & Rx Controller Interface
· ■ EVT 2.1 or 3.0 Format Parser
· ■ Adaptive Time Configuration (SW 알고리즘 제어 방식)
· ■ Event-based Representer and ROI Generator
· ■ Identify the number of event data for the region of interest
Application
· -
Business Area
-
Category

Processor Solutions


Processor Solutions > Vision Processor


Tech Specs
  • IP Name :

    DVS Low-latency & Multi-mode Event-based Signal Processor (차세대지능형반도체사업단)

  • Provider :

    ATUS Inc.

  • Foundry :

    N/A

  • Technology :

    N/A

Deliverables
· ■ Enrypted Netlist, Lib, FPGA Testbench, Datasheet, Integration Guide
Validation Status
· ■ Plan /Developing /Full Simulation / FPGA Verification
Availability
Available
Functional Diagram
Benefits
·
List