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Dynamic Voltage Scaling Digital-LDO

· LDOs are actively used in recent high-performance processors, low-power processors, and SoCs due to their advantages of a small footprint and clean output voltage. In pursuit of efficient design in terms of chip area and power consumption, LDOs are sometimes integrated into SoCs. However, with the ongoing trend of advancing manufacturing processes, traditional Analog-LDOs face challenges in designing at lower VDD levels in fine processes, posing difficulties for SoCs integration. On the other hand, Digital-LDOs leverage the benefits of fine processes, offering improved performance and ease of SoCs integration.

Feature
· (1) Operating Temperature: -40 ~ +125°C
· (2) Supply Voltage: 0.7V – 1.1V (DVDD), 0.7V – 1.1V (VIN)
· (3) Maximum Frequency: 300 MHz
· (4) Quiescent Current: 85 uA (Normal Operation)
Application
· SoC
Business Area
As an on-chip PMIC, it is used for fine-grained power management of SoCs manufactured using the scaled-down process.
Category

Other


Tech Specs
  • IP Name :

    Dynamic Voltage Scaling Digital-LDO

  • Provider :

    POSTECH PICTUS Lab

  • Foundry :

    SAMSUNG

  • Technology :

    28nm

Deliverables
· Datasheet
· Integration application note
· Characterization report
· Hard GDS (GDSII)
· Layout versus schematic (LVS) verification netlist
· Design rule check (DRC) report file
Validation Status
· Testing in progress
Availability
Testing in progress
Functional Diagram
Benefits
· The power efficiency is excellent because it can maintain smaller dropout voltage compared to Analog-LDO
· Easy thermal management of SoC through fine-grained power management
· Because dropout voltage is small, VDD of digital loads such as processors and memory can be increased to maximize performance
· The size of the power transistor is small because it operates as a power switch
· As semiconductor manufacturing process scale down, unlike existing PMICs, there are no difficulties in circuit design and the performance is better.
List