IP 검색 Layout automation framework for current bias DAC (차세대지능형반도체사업단) · 아날로그 회로의 동작 조건을 제어하기 위한 전류 DAC (IP) · 아날로그 회로 및 레이아웃 생성 프레임워크를 활용 자동 생성 Feature · 6 bit 출력· 1mA max current· 76x30um2 area · <0.1LSB INL Application · SoC Business Area High-Speed SerDes Interface Category Analog & Mixed Signal > D/A Converter > Other Tech Specs IP Name : Layout automation framework for current bias DAC (차세대지능형반도체사업단) Provider : Seoul National University Foundry : Others Technology : 7nm Deliverables · GDS Validation Status · Full Simulation Availability Available Functional Diagram Benefits · <0.1LSB INL List Contact Provider 즐겨찾기 등록
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