The Hybrid D Flip-Flop (Hybrid D-FF) is a compact, low-power, fully digital sequential logic IP designed for near-threshold computing (NTC) systems. It is implemented in a 28 nm low-power CMOS process and operates reliably down to 0.25 V, making it ideal for energy-efficient SoCs and low-voltage digital platforms. The flip-flop is fully compatible with standard digital design flows and require no external biasing or control signals beyond the clock (CK) and data (D) inputs.
This flip-flop features a hybrid architecture that combines the robustness of transmission-gate flip-flops (TGFF) with the speed and simplicity of true single-phase clock (TSPC) logic. The design utilizes both feedback and feedforward paths to improve data stability and reduce output delays. The input (D) is sampled on the rising edge of the clock (CK), and the output (Q) is updated accordingly. No asynchronous set or reset is included, allowing for minimal area and power overhead.
Structurally, the Hybrid-FF is composed of a small number of transistors (20 total, including clock inverters), a split TSPC-style latch, and a compact clocking scheme that ensures full voltage transitions without contention. The latch stage employs a feedback loop for stability and a carefully tuned capacitance path to minimize clock-to-Q delay. Architecture eliminates the Vth drop issue commonly found in TSPC designs and ensures full-swing outputs under low voltage.