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[강연 안내]인공지능 반도체 최고경영자 과정(온라인) 개최
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KAIST AI-PIM PIM반도체연구센터

IP 검색

PLL-based clock generator for PIM

· The frequency synthesizer generates a range of frequencies from a single reference frequency, which usually comes from a crystal oscillator. Frequency synthesizers are one of the most critical building blocks in modern electronic devices, such as mobile telephones, laptops, televisions, radiotelephones, satellite communications, GPS systems, etc. One of the popular types of frequency synthesizers is a phase-locked loop (PLL). In Processing-in-Memory (PIM), PLL will be designed and used to synchronize a clock inside the PIM.

Feature
· (1) Operating Temperature: -40 ~ +125°C
· (2) Supply Voltage: 1.8V (vdd_high), 1.5V (vdd_mid), and 1.0V (vdd_core)
· (3) Maximum frequency: 3 GHz – 4 GHz
· (4) Power consumption: < 20 mW (Normal Operation)
· (5) RMS jitter: < 250fs
Application
· SoC
Business Area
Existing and emerging wireless/wired communications
Category
Analog & Mixed Signal > PLL > PLL-based Clock Generator
Tech Specs
  • IP Name :

    PLL-based clock generator for PIM

  • Provider :

    UNIST ACE Lab

  • Foundry :

    SAMSUNG

  • Technology :

    28nm

Deliverables
· Schematic
· GDSII
· Documentation: Datasheet, User Guide
Validation Status
· Lab Test
Availability
Available
Functional Diagram
Benefits
· Wide range of clock frequency supported
· Saving power by DVFS
· Small silicon area
· Industry-beating area
· Competitive noise performance
· To support clean clock for PIM
List