주메뉴 바로가기 본문 바로가기

POPUP ZONE

알기쉬운 AI 반도체 팝업
[강연 안내]인공지능 반도체 최고경영자 과정(온라인) 개최
회원 개인정보 추가 작성 요청
KAIST AI-PIM PIM반도체연구센터

PIM IP

IP 검색

Ring Oscillater based All-Digital PLL (차세대지능형반도체사업단)

· PCIe interface system의 low frequency clock generation 지원 가능한 Ring Oscillator based ADPLL

Feature
· 5GHz clock generation with low phase noise
· Ring oscillator based ADPLL
Application
· SoC
Business Area
High-Speed SerDes Interface
Category
Analog & Mixed Signal > PLL > Other
Tech Specs
  • IP Name :

    Ring Oscillater based All-Digital PLL (차세대지능형반도체사업단)

  • Provider :

    Seoul National University

  • Foundry :

    Others

  • Technology :

    7nm

Deliverables
· GDS, Verification testbench
Validation Status
· Full Simulation
Availability
Available
Functional Diagram
Benefits
· low phase noise
List