The Power-On Reset (POR) circuit is an analog IP designed to generate a reliable reset signal during both power-up and power-down sequences. Implemented in a standard CMOS process, this IP ensures that digital and mixed-signal systems remain in a known safe state until the supply voltage reaches a stable threshold, enabling robust startup behavior across a wide range of conditions.
The POR IP is composed entirely of analog building blocks and requires no external clock, biasing, or digital input control. It receives a single analog input (VDD) and outputs a digital reset signal (VOUT). The core signal path consists of a voltage divider, temperature compensator, and reset signal generator. The voltage divider provides a scalable reference for comparison, while the temperature compensator suppresses variations in threshold voltage due to temperature changes. The reset signal generator includes a carefully sized inverter chain with embedded hysteresis for stable switching behavior.
The circuit is designed to generate the reset signal when the supply voltage crosses a defined rising threshold during power-up, and to reassert the reset during power-down when the voltage drops below a falling threshold. The built-in hysteresis ensures noise immunity and eliminates false resets due to supply ripples or slow ramping.