IP 검색 2차원 합성곱 (차세대지능형반도체사업단) ■ 딥러링 추론(Inference) 시, 2차원 합성곱(Convolution) 유닛(IP) ■ NPU의 Subblock IP Feature · ■ mulit-channel· ■ AMBA AXI interface· ■ 32-bit floating point datatype Application · - Business Area - Category Arithmetic & Mathematic IP Arithmetic & Mathematic IP > Datapath Tech Specs IP Name : 2차원 합성곱 (차세대지능형반도체사업단) Provider : Future Design Systems Foundry : N/A Technology : FPGA Deliverables · ■ Verilog RTL Validation Status · ■ Full Simulation / FPGA Proven Availability Available Functional Diagram Benefits · Datasheet List Contact Provider 즐겨찾기 등록
