This document is intended to provide a systematic description of the LPDDR4 memory controller, including its architecture, functions, interfaces, operating behavior, and limitations, so that designers, verification engineers, FPGA/SoC integration engineers, and software developers can accurately understand and effectively use the IP.
In addition, this document provides the hardware connection information, configuration items, initialization procedures, and reference information required for system integration, thereby improving design efficiency and reducing possible misunderstandings during development and verification.
Feature
· 1) Value added features
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- Support for dual native host ports
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- Parallel processing based on an 8-bank machine architecture
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- Programmable timing registers
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- Built-in refresh control
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- Masked write support
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2) Programmability
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- Read/write latency configuration
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- Refresh timing configuration
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- Bank machine timing parameter configuration
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- Command phase selection
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- Scheduler timing parameter configuration
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3) Optimal external memory accesses
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- Bank-based scheduling for improved parallelism
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- Crossbar-based request distribution
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- Command multiplexing for efficient PHY utilization
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- Configurable read/write timing for throughput optimization
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- Refresh insertion with minimized interference to normal accesses
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4) Power related signal
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- LPDDR4 control signal support such as cke and reset_n
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- PHY-side interface signals related to DRAM control
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- Detailed low-power mode behavior is implementation-dependent
Business Area
Memory Controller / Semiconductor IP
Tech Specs
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IP Name :
LPDDR4/X Memory Controller(for palladium emulation only)
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Provider :
KAIST PIM Semiconductor Design Research Center
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FPGA Device :
Lattice Avant-E Evaluation Board
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Foundry :
N/A
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Bus Compliance :
AXI, AHB, DFI 5.0, LPDDR4/4X
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Technology :
N/A
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Compliant Standard :
JEDEC
Deliverables
· RTL source code of the LPDDR4/4X memory controller, including controller core, AXI/native interface blocks, DFI adapter, crossbar, bank machine, multiplexer modules.
Validation Status
· Validated in a Palladium-based emulation environment with functional verification of controller operation and interface connectivity. Ongoing work includes FPGA implementation and physical LPDDR4 device control, along with continued improvement of code coverage, functional coverage, and assertion-based verification.
Availability
Available for Palladium-based emulation and FPGA implementation.
Benefits
· Provides a Palladium-optimized LPDDR4/4X memory controller for fast design validation and long-duration test scenarios. Supports AXI-to-DFI based integration, enables realistic memory access verification in emulation environments, and can be extended toward FPGA-based control of physical LPDDR4 devices.
