IP 검색 Category Analog & Mixed Signal(28) Memory Controller & PHY(12) Memory & Logic Library(14) Interface Controller & PHY(22) Processor Solutions(38) Arithmetic & Mathematic IP(3) Peripheral(8) Network-on-Chip (NoC)(0) Multimedia(0) Comumnication(0) Platform Level IP(0) Security IP(1) Other IP(0) Software Development & Debug Tool(3) Other(29) Verification IP(12) Technology 3nm 4nm 5nm 7nm 8nm 10nm 12nm 14nm 16nm 20nm 22nm 28nm 32nm 40nm 45nm 55nm 65nm 90nm 130nm 150nm 180nm 250nm 350nm 500nm FPGA N/A Foundry Others N/A Search IP 전체 제목 내용 검색 전체 136건 현재 페이지 23/34 Level Shifter • The proposed level shifter, named the diode-connected cross coupled pFET level shifter with staked split-input inverter (DCPLS-SSI) is a wide-range voltage conversion and energy-efficient solution for DRAM voltage conversion in 28 nm CMOS technology. The proposed level shifter can mitigate the current contention by using diode-connected cross coupled pFET structure, which enables wide-range voltage conversion. In addition, the stacked split-input inverter can reduce the short-circuit current of output inverter, which enable energy-efficient operation. 2025-07-04 Low Power Object Detection Forward Process Unit (Tiny-YOLOv3) (차세대지능형반도체사업단) · High-throughput/Low-power Tiny YOLOv3 추론을 위한 외부 메모리 접근을 최소화한 recursive architecture 기반 가속기 유닛(IP) 2024-08-29 Low-bit 추론 가속기 (Low-bit Inference Accelerator) · 딥러닝 경량(1/2bit) 추론(Inference)을 고속 처리하기 위한 HW 가속기 IP 2024-08-29 LPDDR4/X Memory Controller(for palladium emulation only) This document is intended to provide a systematic description of the LPDDR4 memory controller, including its architecture, functions, interfaces, operating behavior, and limitations, so that designers, verification engineers, FPGA/SoC integration engineers, and software developers can accurately understand and effectively use the IP. In addition, this document provides the hardware connection information, configuration items, initialization procedures, and reference information required for system integration, thereby improving design efficiency and reducing possible misunderstandings during development and verification. 2026-03-23 처음으로 이전페이지 18 19 20 21 22 23 24 25 26 27 >다음페이지 마지막으로
