Feature
· • Fabricated in Samsung 28 nm LPP CMOS process
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• Implemented with analog low-Vth (anglvt) devices
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• Single-stage, 5-transistor voltage-mode amplifier optimized for feedback loops
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• IP area: 7.09 µm2
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• Input common-mode range: 250 mV to 750 mV
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• Single-ended output swing: 200 mV to 800 mV, linear across the full input range
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• Supply voltage: 0.9 V to 1.1 V
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• Operating temperature: -20 °C to +85 °C
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• No internal bias generation—external VBIAS must be provided to establish a 1 µA tail current
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• Layout uses metals up to M4, preserving upper layers for top-level routing
Application
· • Capacitor-based analog value storage with voltage feedback loop
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• Feedback amplifierr for charge-h
Deliverables
· Schematic netlist & testbench