IP 검색 Category Analog & Mixed Signal(29) Memory Controller & PHY(13) Memory & Logic Library(14) Interface Controller & PHY(22) Processor Solutions(38) Arithmetic & Mathematic IP(3) Peripheral(8) Network-on-Chip (NoC)(0) Multimedia(0) Comumnication(0) Platform Level IP(0) Security IP(1) Other IP(0) Software Development & Debug Tool(3) Other(29) Verification IP(12) Palladium(0) Technology 3nm 4nm 5nm 7nm 8nm 10nm 12nm 14nm 16nm 20nm 22nm 28nm 32nm 40nm 45nm 55nm 65nm 90nm 130nm 150nm 180nm 250nm 350nm 500nm FPGA N/A Foundry Others N/A Search IP 전체 제목 내용 검색 전체 138건 현재 페이지 1/35 최신 순 오래된 순 PLL This PLL IP is an ADPLL-based analog/mixed-signal clock generation IP designed for high-speed SoC and ASIC clock-management applications. It operates in normal 1:1 frequency mode, where the output clock frequency follows the input reference-clock frequency. The supported operating frequency range is from 1 GHz to 4.4 GHz. The PLL consists of a Time-to-Digital Converter (TDC), Frequency Detector (FD), Digital Loop Filter (DLF), 11-bit Digitally Controlled Oscillator (DCO), high-PSRR reference generator, level shifter, optional divide-by-2 path, and feedback path. It provides differential output clocks through PLL_CLK[1:0] and supports frequency setting, loop-gain adjustment, oscillator calibration, BIST, and test-control functions. The IP is designed for Samsung Foundry 28 nm LPP process with M1–M6 + IA/IB metal stack option. It is suitable for high-speed clock regeneration, phase alignment, and low-jitter clock distribution in digital and mixed-signal SoC systems. 2026-07-24 LPDDR4/X PHY(for palladium emulation only) This IP is an LPDDR4/LPDDR4X PHY developed by our team based on LiteDRAM. It extends the LiteDRAM-based architecture with our own design and integration to support controller-side DFI interfacing, command/data serialization, and LPDDR4/LPDDR4X physical signaling for emulation-oriented system validation. 2026-03-26 LPDDR4/X Memory Controller(for palladium emulation only) This document is intended to provide a systematic description of the LPDDR4 memory controller, including its architecture, functions, interfaces, operating behavior, and limitations, so that designers, verification engineers, FPGA/SoC integration engineers, and software developers can accurately understand and effectively use the IP. In addition, this document provides the hardware connection information, configuration items, initialization procedures, and reference information required for system integration, thereby improving design efficiency and reducing possible misunderstandings during development and verification. 2026-03-23 Compact Full-Rate Receiver Front-Ends Full-Rate Receiver This IP is compact single-ended receiver front-ends generated by layout generator software. This IP adopts quarter-rate architecture. The front-ends uses half-VDD termination and received bit errors can be checked and counted real time by PRBS Checker. Termination resistance can be tuned using resistor bank controlled by digital bits. Slicers reference voltage can be controlled by external analog voltage input. Precise control for duty cycle and quarter-rate phase mismatch can be achieved by DCC and QEC blocks. The front end’s generation time is only 0.713s which is 240000 times fast than manual layout. 2026-02-27 처음으로 이전페이지 1 2 3 4 5 6 7 8 9 10 >다음페이지 마지막으로
